This invention relates to programmable logic array drivers, and in particular to a programmable logic array driver which provides a first drive capability to a row line during normal operation of the device, and a second drive capability to the row line during programming, as well as optimal low voltage output (VOL) levels for both normal and programming modes.
Programmable logic arrays (PLAs) are well known in the prior art. They include an array of programmable elements which may comprise, for example, fuses made of titanium tungsten, nichrome, or polycrystalline silicon, or transistor devices capable of being shorted when a programming current is applied. Such an array of programmable elements, arranged in a pattern of rows and columns, is programmed by a user to provide a specific pattern for providing desired output signals in response to input signals.
Such programmable logic array devices include a number of PLA drivers for driving the row lines. These drivers must accomplish two tasks. First, during normal operating conditions, they must provide a logical one or logical zero signal to the row line, depending upon the state of a related input signal. A sense amplifier is connected to the bit lines to determine if the programmable element located at the intersection of a row line and bit line has or has not been programmed.
Secondly, during programming, the PLA driver must provide sufficient current to the row line to cause a selected programmable element to be programmed. Of importance, the amount of current required to be supplied by the PLA driver to the row line is considerably less during normal operation (typically 20-30 milliamps) as compared with the current required to be provided to a row line during programming (typically 60 milliamps).
A simple form of row driver is a standard TTL totem pole output stage, as shown in FIG. 1, which can be made to provide adequate current to row line R1 during programming and during normal operation, although this requires a considerable amount of power during the programming mode. However, this rather simple PLA driver structure has inherent disadvantages. For example, since this type of PLA driver must sink large amounts of current in the programming mode, it will sink approximately 60 ma in both the programming and normal operating modes of the device. In addition, this type of PLA driver is inherently slow during normal operation of the device, since its components must be large and therefore have relatively large capacitance.
Another prior art PLA row driver is shown in FIG. 2. This PLA driver includes a TTL totem pole output circuit, plus the addition of Schottky diode 21 or similar device connected between the base of transistor 22 and output terminal 23. When the output signal on terminal 23 connected to row line RW1 goes low due to conduction of pull-down transistor 24, diode 21 becomes forward biased, thereby reducing the signal applied to the base of transistor 22, which in turn reduces the drive available to pull-down transistor 24. This voltage feedback provided by the addition of diode 21 reduces the drive to pull-down transistor 24 when the output signal on terminal 23 reaches the logical zero level, thereby keeping transistor 22 operating in the linear mode. Phase splitter transistor 26 provides voltage levels required to operate pullup transistor 27. Thus the circuit of FIG. 2 keeps transistor 22 operating in the linear mode, reducing base drive to pull-down transistor 24, allowing transistor 24 to turn off more rapidly.
However, the circuit of FIG. 2 suffers from transient ringing of the output signal on terminal 23 due to the phase lag of signals propagated through the feedback loop provided by diode 21. Transient ringing on a signal makes it difficult to determine the level of the signal, since its voltage is changing. In the circuit of FIG. 2, the logical zero output signal VOL on terminal 23 is equal to V.sub.be (Q24) plus V.sub.be (Q22) minus V.sub.D (D21), or about 1.0 to 1.2 volts. This VOL signal is relatively high, which must be properly sensed by a sense amplifier (e.g., sense amplifiers S1 and S2 connected to monitor levels on bit lines B1 and B2, respectively) reducing the voltage swing between a logical zero and a logical one. Furthermore, this VOL level is temperature dependent, since it is dependent on V.sub.be which, as is well known, is itself dependent on temperature. This circuit provides a logical one voltage level VOH approximately equal to V.sub.cc V.sub.be (Q27)-V.sub.D (D28). Particularly at low temperatures, the transition between VOL and VOH becomes rather small, requiring a more sensitive sense amplifier connected to each bit line to properly distinguish between a logical zero and a logical one.
In an alternative form of prior art PLA row driver (FIG. 3), two separate pull-down transistors Q4 and Q6 are used in a TTL totem pole row driver configuration. Programming pull-down transistor Q6 is a large device which is enabled during programming in order to sink a sufficient amount of current in order to program programmable elements F1, F2 connected to row line RW1. Normal operation pull-down transistor Q4 is smaller in size than programming pull-down transistor Q6 and is enabled during normal operation. Although a larger transistor Q6 is utilized for programming, it is still connected to row line RW1, and thus its capacitance remains connected to row line RW1 during normal operation, thereby having a detrimental effect on speed during normal operation. However, utilizing this type of prior art PLA row driver, power consumption is reduced and two separate VOL levels are achieved, one associated with normal operation of the device, and the other associated with programming. However, in a PLA device, the current which must be sunk by a row driver during normal operation can be relatively high, due to a relatively large number of programmable elements which may be connected to the row line at any given time. This prior art approach is more suitable for use in programmable read only memories (PROMs) in which during the read operation only a single programmable element, at most, will conduct current to the row line driver. Thus, in PROMs, the pull-down transistor used during normal operation can be made extremely small, thereby providing a significant speed and area advantage, far greater than is possible when using this technique to provide a row driver for use in a PLA. While this technique is operable in PLAs, it adds additional area to an integrated circuit device, as well as adding additional stray capacitances.
In another prior art PLA driver (FIG. 4), the pull-down transistor of a standard TTL totem pole is replaced by a Darlington pair (Q50, Q51). The Darlington pair allows a single transistor set to perform the pulldown function during both normal operating and programming modes. Unfortunately, wih this circuit during normal operation a logical zero on row line RW1 is equal to V.sub.be (Q50) +V.sub.sat (Q51), or about 1.0 to 1.2 volts. This is an undesirably high threshold level for a logical zero signal during normal operation. During normal operation, this relatively high voltage level associated with a logical zero limits the operating range of the device by reducing the voltage margins of the circuit. However, this logical zero level has an advantage during programming by making the device less prone to latch-up caused by conduction of parasitic SCR devices which are inherently formed between the semiconductor tubs containing adjacent rows.
Another prior art PLA driver is shown in the schematic diagram of FIG. 5. This prior art circuit uses two separate subcircuits for driving row line RW1, one for normal operation and one for programming. PLA driver 10 of FIG. 5 includes a standard TTL totem pole driver circuit formed by transistors Q1, Q2, Q3, and Q4 together with associated components in order to drive row line RW1 during normal operation of the device. As shown in FIG. 5, fuse devices F1 and F2 are connected between row line RW1 and bit lines B1 and B2, respectively, Thus, during normal operation, the TTL totem pole circuit provides the appropriate logic level to row line RW1 in response to the logic level of the input signal applied to input terminal IN1, in much the same manner as in the circuit of FIG. 1. During programming, PLA driver 10 uses the Darlington pair formed by transistors Q5 and Q6 to drive row line RW1. Darlington pair Q5, Q5 turns on when the base of transistor Q5 is held high by the address signals applied to the decoding circuitry formed by diodes D1, D2, D3 and resistor R7 connected to V.sub.cc .
In this manner a single, standard TTL pull-down device Q4 is used to pull-down row line RW1 as needed during normal operation, and Darlington pair Q5, Q6 is used to pull-down row line RW1 during programming. During normal operation, a logical zero on row line RW1 is equal to V.sub.sat (Q4); during programming a logical zero on row line RW1 is equivalent to V.sub.sat (Q5)+V.sub.be (Q6). The disadvantage of the circuit of FIG. 5 is that three transistors (Q4, Q5 and Q6) are required to pull down row line RW1: transistor Q4 during normal operation and transistors Q5 and Q6 during programming. This requires additional surface area on the integrated circuit and adds stray capacitance to the device. Furthermore, transistors Q4 and Q6 are both rather large, requiring additional surface area and adding capacitance to row line RW1 with a corresponding decrease in speed.